Lesson #3 transistor biasing for designing amplifiers part 1

OK, Let's actually make an amplifier, with 2n3904 transistors. And lets drive a miniature 8 ohm speaker.

First off, an 8 ohm speaker is a very low impedance, however not to worry,,,,we now know how to design DC amplifiers.
OK so what do we do,,well we have learned that transistor amps, have three configurations, CE,CB,CC, and we know the parameters of each these configs.

So we use these configs as building blocks, if we want highZ input and low Zoutput we use a CC. amp.
If we want maximum voltage amplification, we use CE amp. and so on...

An 8 ohm load is very low impedance, so we should start out by using an CC amp stage, so as to give ourselves some high Zin into it, and let it drive the spkr, with loads of current at the same time. (as a CC. has high current gain)

Design steps:

1) Pick a transistor (2n3904 this case) and read its data sheet on max. power diss. (650mW this case)
Choose to use a value well below it, I chose around 400mW to see how it would work.

2) calculate the current the transistor will take with the power diss. you chose. (my case around 105mA)
divide that current so the (PK-PK) current through the load branch is around 1.3 to 1.5 times smaller than the emitter resistor branch.
from there you calculate a value for the emitter resistor.

Now looking at the picture below. you notice the colector current is around 59mA, that is correct, it is the DC bias current through the emitter branch. The rest of the calculated current flows through the load calculated as the Pk-Pk voltage across the 8 ohm load.
Because the load is capacitive coupled in only sees the AC current of the original calculated collector current value, from step #2.

The calculated value across the 8 ohm load is around 360mV pK-pK, if I can get that value across the 8 ohm spkr load, it will have sufficient power output in the spkr, to be audible enough to hear a signal generated frequency.

3). build the circuit as shown and check key bias voltages (around 1/2 Vcc across the emitter resistor), then input a signal large enough to check for non distorted output at around 360mV pk-pk.



Now let's analyse the input impedance, first for ballpark estimates we will disregard the ("re" value) and just look at physical resistors.
We have a 68 ohm resistor in parallel with an 8 ohm resistance, once we solve for that parallel combo. we then take that value times an assumed beta of 100 to give the Zin of this stage. Roughly this case less than 800 ohms.

Ok so we brought the 8 ohm impedance up to around 800 ohms, but that's still to low we need another high Zin, so lets DC couple another CC amp to it. So far we don't want any ac coupling just yet. So if DC it is, we take the base bias resistor of Q1, and replace it with a transistor CC amp stage.

To do this you, have learned how to bias a transistor for any amount of reasonable current you need, so measure and calculate the current flow through the base resistor of Q1, and bias another CC stage to meet that current requirement.

Here is where you choose your own values for VCE and bias resistors ect... Your goal at this stage is to keep close enough your original output voltage across the emitter resistor that drives the load.



When you build the circuit always at each stage measure values at key locations to make sure your voltages are within the range you were aiming for, if not then always tweek resistor values to get design values of currents and voltages.

Now the input impedance is much higher (in my case around 33000 ohms), now I have substantial Zin to work with.
I brought the 8 ohm load to look like a 33K ohm load, so now I can try to do something with it.

Knowing a CE stage gives amplification, it's time to DC couple a CE stage into this to see if it can amplify as well.
So a CE needs its output to be on the collector side, so I need to replace the value of the grounded resistor (my case 160K ohms), with a CE amp stage.

Again just choose a value of VCE, and go from there to bias the transistor to have the currents and voltages at its output to match the values already present.

Ok where did the 3k ohm resistor come from, I chose to set the emitter voltage and thus the VCE by choosing a value of emitter resistor that would give some gain to the amp. In other words for this amp I chose first of all what gain would I like it to have than chose the emitter resistor to make that gain, than using the already established currents needed, I calculated the bias voltages.

Something to see here, is you need to get comfortable knowing where and when to choose bias arangements.

Up until now I was biasing the stages according to currents and voltages needed, therefore VCE was chosen first, but now I switched gears and chose for this stage I'll let the gain (emitter resistor) determine the VCE still aiming for the design values but in a different approach to find that value.



Ok now it's all built its time to test it with a AC signal and analyse it.



I'm getting my design output voltage and some.

I'm looking for a pK-pK output across the 8 ohm load of around 360mV.
As I input a signal of around 240mV input I'm getting a non distorted output swing of around 540mV.
Ok design succesful.

pic 1

pic 2

However lets do some analysing, and see why such a low gain from input to output.

Time to do an analysis on it.

1). lets see how were doing for voltage gain (Av) on the CE stage. (1.8v output pk-pk.) (Av ~= 7.5)



Ok how much drop in voltage is the Q2 load doing to Q3 stage. (2.05v output pk-pk) (Av ~= 8.5)
That shows any small bit of load has an effect on gain of the stage.



Ok so when we hook up the Q2 load to Q3, we have a small voltage drop, so Q2 is not the cause of a significant drop at the output of Q1 stage.

However if we probe further on the other side of the 1.6K ohm resistor, we find the culprit (max voltage drop)



(voltage output dropped from 1.8V pk-pk to 540mV pk-pk.) That's where we need to start our redesign, if we want to get a larger gain from input to output.)

Very important, do not miss this point:
We are not trying to drive more power into the 8 ohm load of Q1, we have our maximum design power requirement, plus some, we are trying to get more small signal amplification. If we can get the input voltage down further we can use the amplifier to amplify a much smaller input signal.

Ok there are numerous ways to redesign this Q2 stage. We can put the emitter resistor (1.6K ohms) on the collector lead of Q2, maybe that would work (we may need to change its value somewhat) so that;s an option, or lower the emitter resistor value, then recalculate bias resistors for Q3 stage, or put a emitter bypass capacitor across the 1.6K ohm resistor. ect...
It's up to you to experiment and make decisions of what to do with it.

I'm choosing to keep the high emitter resistor of 1.6K ohms for the purpose of negative feedback which helps with increasing the bandwidth among other factors. So I'm going to elect to use a bypass capacitor, so as to keep some neg. feedback on the DC level, but reduce the AC neg. feedback, because it's the AC content that I'm trying to amplify.

So I could choose to go through the calculations of finding the XC at the lowest frequency that will work with the Zin of the Q2 stage, and so on, or at this point just throw in a large capacitor and see what kind of sgnal input to output gain I could get.

I'm going to bypass all the calculation stuff and just insert a capacitor across the resistor and see what happens.



As expected we got Distortion that's a good thing, because we want to drive it with a smaller input signal.
Lets experiment with lowering input voltage,



lowered it from 240mV pk-pk to 100mV pk-pk.



So now this whole circuit can be used as a low power, low impedance output, high impedance, small signal input, buffer amplifier.

I can drive an 1wt. 8 ohm spkr. with reletively flat bandwidth across the audio range, with a input signal in the 100's mV range.
By designing the DC portions of the amp with transistors acting as current sources for the biasing of the stages Q1, and Q2, allowed me to turn an 8 ohm spkr load into a ~ 200K ohm input load, presented to any CE preamp that would be coupled to the input of this circuit.

One last modification to drive home this lesson in biasing transistors, let's throw in there a CE. preamp, and see if we can get the input signal down lower yet.

Design procedure:

The input signal is around 160mV pk-pk.
So I'll design for a gain of 40, and hope I get at least 50% of it, on the final output. Because there is going to be signal loss before it reaches the Q1 stage, so design for a higher gain than expected, than tweek values.

Now design a CE preamp stage.

The Zin of this circuit is maybe around ~= 200K ohms.
Choose a collector resistor about 1/10 of it, around 20K ohms.
Now (20K / 40) would be the emitter resistor for a gain of ~40 for this preamp stage. This is around 510 ohm resistor.
I'll make the base to ground resistor around 10 times greater, or 5.1K ohms., If I needed to match an impedance of the driving source with high output, then I would have to calculate using that value. My case my audio gen. is around 600 ohms Zout.
So now the other resistor value is calculated and the circuit built and tweeked and here is the result:

Av ~= 135, I can go as low as around 2mV pk-pk signal and get 270mVpk-pk. Were in the design range for power to the spkr load.
So now the input waveform amplitude was reduced from 100mVpk-pk, to, 2mVpk-pk.



However that's all simulated results with perfect parts and electrical environment.


Therefor all this means nothing if the results can't be realized with an actual breadboarded circuit with real imperial measurements.

Here is the pics of the real circuit performance.

NOTE:........................

Due to limit of files to upload, the actual circuit, pictures of the circuit and waveforms on a real oscilloscope, are in the following blog.